The present invention relates to a bus interface control system and apparatus for a data transfer in a multiprocessor system in which a plurality of MPUs, a plurality of IOCs and a common memory are connected to a system bus.
Generally, in a computer system having two different buses, it is necessary to provide a bus interface between the two buses. For example, in a multiprocessor system, a plurality of microprocessors (MPUs), a memory and an input/output unit (I/O unit) which are resources in common for the MPUs have first buses. The first buses are mutually connected via a second bus provided in common for the above elements. Normally, the first buses are called local buses, and the second bus is called a system bus. Bus interfaces are provided for the respective local buses, and connect the respective local buses to the system bus.
In order to improve the system performance in recent computer systems, the amount of information (address and a series of data) in a once transfer sequence tends to be increased in recent computer systems.
FIG. 1 is a diagram showing the outline of a system to which the present invention can be applied. A computer system shown in FIG. 1 has a plurality of first buses (local buses) 13 and 14, and a second bus 5 (system bus). These buses are provided for transferring information. An MPU 1 is connected to the first bus 13, and a memory (MEM) 6 is connected to the first bus 14. Similarly, other elements are connected to the first buses.
The first bus 13 and the second bus 5 are mutually connected via a bus interface (BIF) 10, and the second bus 14 and the second bus 5 are mutually connected via a bus interface (BIF) 11.
In a case where data is transferred between the MPU and the memory, a memory controller is disposed between the MPU and the memory. The memory controller serves as an interface between the MPU and the memory. FIG. 2 shows a data transfer which is carried out between the MPU and the memory. Normally, a cache memory 1a is built in the MPU 1 in order to compensate for a low-speed operation of the memory 2. In order to store data read out from the memory 2, it is necessary to provide a memory controller 3 with a buffer memory 3a having a capacity necessary for a replacement control to the cache memory 1a.
The MPU 1 having the cache memory (hereinafter referred to as a buffer) 1a carries out a block transfer to replace the contents of the buffer 1a. The unit of the block transfer is 4 W (16 bytes), assuming that one word (W) is equal to 4 bytes. The memory controller 3 has a 16-byte buffer to realize the block transfer, and sequentially sends data necessary for an initial stage of the block transfer to the MPU 1.
Generally, in a multiprocessor system as shown in FIG. 3, a common memory 6, a plurality of MPUs 7 and an IOC (input/output control unit) 8 are connected to the system bus 5. The data processing ability of the entire system is limited by the throughput of the system bus 5. In order to improve the throughput, a synchronous type time split method is employed. In a conventional synchronous type time split method, information is transferred in synchronism with a clock, and an interface between a request and an answer is split on the time base. A large storage capacity buffer is provided for a bus interface (BIF) in order to accomplish such a synchronous type time slit method. By using the above synchronous type time split method, it is possible to use idle portions for an arbitrary purpose.
Turning now to FIG. 3, the MPU 7 transfers a read command C and an address A to the common memory 6, which returns read data D, D, D, . . . to the MPU 7 together with an answer AN. The read command C includes information indicative of the number of bytes of data requested to be transferred, and information representative of the read request.
A description will now be given of an MPU accessing procedure and an IOC accessing procedure in conventional multiprocessor systems with reference to FIG. 4, in which those parts which are the same as those shown in FIG. 3 are given the same reference numerals. A local bus 13 is provided between the MPU 7 and a bus interface 10. The system bus 5 is provided between the bus interface 10 and the bus interface 11. A local bus 14 is provided between the bus interface 11 and a memory controller 12. The memory controller 12 is connected to the common memory 6.
In response to a block transfer request which is output by the MPU 7 and received by the bus interface 10 via the local bus 13, the bus interface 10 sends the read command C and the address A of the common memory 6 to the bus interface via the system bus 5. The bus interface 11 transfers the block transfer request from the MPU 7 to the memory controller 12 via the local bus 14.
The memory controller 12 reads out data amounting to one block (4 W; four words) from a storage area of the common memory 6 designated by the address A, and temporarily stores the readout data in an internal buffer having a storage capacity equal to 4 W. After that, the memory controller 12 sends the one-block data to the bus interface 11 via the local bus 14. The bus interface 11 transfers the answer AN and data D1-D4 amounting to 4 W to the bus interface 10 via the system bus 5. The MPU 7 receives the data D1-D4 amounting to 4 W output from the bus interface 10 via the local bus 13, and stores the received data in a cache memory (not shown) provided therein.
FIG. 5 is a diagram illustrating the IOC accessing procedure. In FIG. 5, those parts which are the same as those shown in FIG. 4 are given the same reference numerals. In the IOC accessing procedure, a burst transfer of data is carried out instead of the block transfer. The burst transfer is capable of transferring a large amount of data at one time, so that an efficient data transmission can be realized.
In response to a burst transfer request which is generated and output by the IOC 15 and received by the bus interface 10 via the local bus 13, the bus interface 10 sends the read command C and the address A of the common memory 6 to the bus interface 11 via the system bus 5. The bus interface 11 transfers the burst transfer request from the IOC 15 to the memory controller 12 via the local bus 14.
The memory controller 12 successively reads out data from a storage area of the common memory 6 designated by the address A, and temporarily stores the readout data in an internal buffer memory (having a storage capacity equal to NW). Then, the memory controller 12 sends the readout data to the bus interface 11 via the local bus 14. The bus interface 11 sends the answer An and data D1-DN amounting to NW to the bus interface 10 via the system bus 5. The IOC 15 receives the data via the bus interface 10, and successively stores the internal memory (not shown), and successively carries out a predetermined data processing.
As has been described previously, the memory controller 12 has the internal buffer amounting to 4 W for use in the block transfer, and realizes the high-speed data transfer. Further, in order to realize the burst transfer using the IOC 15, the memory controller 12 needs the internal buffer amounting to NW used for converting the bit rate. This leads to an increase in the amount of hardware of the memory controller 12. In some cases, the bit rate of the block transfer is sacrified. Generally, in many cases, the common memory 6 is accessed by the MPU, and is not frequently accessed by the IOC. It is not efficient to provide for the internal buffer amounting to NW in the memory controller in order to realize a little frequency of accessing by the IOC.